Search for: All records

This paper presents a novel approach employing localized annealing through Joule heating to enhance the performance of Thin-Film Piezoelectric-on-Silicon (TPoS) MEMS resonators that are crucial for applications in sensing, energy harvesting, frequency filtering, and timing control. Despite recent advancements, piezoelectric MEMS resonators still suffer from anchor-related energy losses and limited quality factors (Qs), posing significant challenges for high-performance applications. This study investigates interface modification to boost the quality factor (Q) and reduce the motional resistance, thus improving the electromechanical coupling coefficient and reducing insertion loss. To balance the trade-off between device miniaturization and performance, this work uniquely applies DC current-induced localized annealing to TPoS MEMS resonators, facilitating metal diffusion at the interface. This process results in the formation of platinum silicide, modifying the resonator’s stiffness and density, consequently enhancing the acoustic velocity and mitigating the side-supporting anchor-related energy dissipations. Experimental results demonstrate a Q-factor enhancement of over 300% (from 916 to 3632) and a reduction in insertion loss by more than 14 dB, underscoring the efficacy of this method for reducing anchor-related dissipations due to the highest annealing temperature at the anchors. The findings not only confirm the feasibility of Joule heating for interface modifications in MEMS resonators but also set a foundation for advancements of this post-fabrication thermal treatment technology. 

This paper presents the first demonstration and comparison of two identical oscillator circuits employing piezoelectric zinc oxide (ZnO) microelectromechanical systems (MEMS) resonators, implemented on conventional printed-circuit-board (PCB) and three-dimensional (3D)-printed acrylonitrile butadiene styrene (ABS) substrates. Both oscillators operate simultaneously at dual frequencies (260 MHz and 437 MHz) without the need for additional circuitry. The MEMS resonators, fabricated on silicon-on-insulator (SOI) wafers, exhibit high-quality factors (Q), ensuring superior phase noise performance. Experimental results indicate that the oscillator packaged using 3D-printed chip-carrier assembly achieves a 2–3 dB improvement in phase noise compared to the PCB-based oscillator, attributed to the ABS substrate’s lower dielectric loss and reduced parasitic effects at radio frequency (RF). Specifically, phase noise values between −84 and −77 dBc/Hz at 1 kHz offset and a noise floor of −163 dBc/Hz at far-from-carrier offset were achieved. Additionally, the 3D-printed ABS-based oscillator delivers notably higher output power (4.575 dBm at 260 MHz and 0.147 dBm at 437 MHz). To facilitate modular characterization, advanced packaging techniques leveraging precise 3D-printed encapsulation with sub-100 μm lateral interconnects were employed. These ensured robust packaging integrity without compromising oscillator performance. Furthermore, a comparison between two transistor technologies—a silicon germanium (SiGe) heterojunction bipolar transistor (HBT) and an enhancement-mode pseudomorphic high-electron-mobility transistor (E-pHEMT)—demonstrated that SiGe HBT transistors provide superior phase noise characteristics at close-to-carrier offset frequencies, with a significant 11 dB improvement observed at 1 kHz offset. These results highlight the promising potential of 3D-printed chip-carrier packaging techniques in high-performance MEMS oscillator applications. 

This study investigates the integration of reduced graphene oxide (rGO) films as ground plane in miniaturized RF/mm-wave systems for advanced thermal management applications. Traditional methods such as copper-based heat spreaders struggle to handle the increased power and tighter integration requirements of modern day RF/mmWave packaging. Due to rGO’s exceptionally high in-plane thermal conductivity (∼1100 W/mK), when compared with copper (∼400 W/mK), rGO emerges as a compelling candidate for thermal management in RF electronic packaging. This study investigates the use of rGO to form a ground plane in RF and microwave electronics, evaluating its performance through meticulous transmission line simulations and measurements. Our findings reveal that rGO ground planes exhibit high signal integrity, with an average loss of about 1 dB at 10 GHz and around 2 dB up to 26 GHz, comparable to the performance of traditional copper ground planes. These results indicate that rGO is a promising material for RF and microwave circuits, especially in applications requiring enhanced thermal management and mechanical flexibility. 

The demand for reconfigurable devices for emerging RF and microwave applications has been growing in recent years, with additive manufacturing and photonic thermal treatment presenting new possibilities to supplement conventional fabrication processes to meet this demand. In this paper, we present the realization and analysis of barium–strontium–titanate-(Ba0.5Sr0.5TiO3)-based ferroelectric variable capacitors (varactors), which are additively deposited on top of conventionally fabricated interdigitated capacitors and enhanced by photonic thermal processing. The ferroelectric solution with suspended BST nanoparticles is deposited on the device using an ambient spray pyrolysis method and is sintered at low temperatures using photonic thermal processing by leveraging the high surface-to-volume ratio of the BST nanoparticles. The deposited film is qualitatively characterized using SEM imaging and XRD measurements, while the varactor devices are quantitatively characterized by using high-frequency RF measurements from 300 MHz to 10 GHz under an applied DC bias voltage ranging from 0 V to 50 V. We observe a maximum tunability of 60.6% at 1 GHz under an applied electric field of 25 kV/mm (25 V/μm). These results show promise for the implementation of photonic thermal processing and additive manufacturing as a means to integrate reconfigurable ferroelectric varactors in flexible electronics or tightly packaged on-chip applications, where a limited thermal budget hinders the conventional thermal processing.